1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly to off-chip driver circuits utilized in integrated circuit devices.
2. Description of the Related Art
Off-chip driver circuits (OCDs) are used to drive a variety of different type signals, such as data and clock signals, out of integrated circuit device (IC), typically onto a bus. To ensure system signal integrity, an OCD has to be designed to meet both DC and AC specifications. While the DC specification defines static characteristics such as drive strength, AC specifications define dynamic characteristics, such as slewrate and propagation delay of the OCD. To ensure that low-to-high (L-H) and high-to-low (H-L) transitions of the OCD (propagation delay, rise and fall times) do not differ too much to each other, acceptable pull-up/pull-down current ratio, as well as pull-up/pull-down slewrate ratio, ranges are specified.
As illustrated in FIG. 1, a conventional OCD circuit 100 typically utilizes two stages: a control (pre-driver) stage 110 and a simple inverter (end driver) stage 120. The control stage 110 typically receives an input signal (IN) and an output enable (OE) signal, which are applied to a NAND gate 112, NOR gate 114, and inverter 116, in order generate a pair of voltage control signals CP and CN. When the OE signal is not asserted, outputs CP and CN of the control stage 110 are in a high-impedance state. When OE is asserted, outputs CP and CN, that are typically an inversion of the input signal IN, are applied to inputs of the end driver stage 120.
The end driver stage 120 receives the signals CP and CN and, in response generates a corresponding output signal VOUT, that is typically a logical inversion thereof (i.e., a non-inverted version of the input signal IN). As illustrated, the end driver stage 120 includes a P-type transistor MP1 122 and an N-type transistor MN1 124, with resistors 126 and 128 to set a desired output impedance when the outputs are disabled (OE de-asserted). With the outputs enabled (OE asserted), as CP and CN transition high, MN1 is turned on and MP1 is turned off. Therefore, the output node is pulled low as current IN1 flows through MN1, thus resulting in a logic low for the output signal OUT. As CP and CN transition low, MN1 is turned off and MP1 is turned on. Therefore, the output node is pulled high as current IP1 flows through MP1, thus resulting in a logic low for the output signal OUT.
Thus, the main purpose of the end driver stage 120 is to drive the input signal IN to the bus (e.g., on a bus line with a representative capacitive load CLOAD), preferably with little difference (or “skew”) between rising and falling edges. One approach to reduce this skew is to tune the size of the transistors used in the end driver stage 120 to match the rate at which the output node is discharged or charged (as current IN1 and IP1 flows, respectively). However, current flow through NMOS and PMOS transistors is highly sensitive to process variations (e.g., variations in supply voltages or operating temperature).
As illustrated in FIG. 2A, process variations resulting in stronger NMOS current drive (relative to PMOS current drive) may result in the output node being pulled down through MN1 faster than it is pulled up through MP1 (resulting, e.g., in a faster discharge rate). Similarly, as illustrated in FIG. 2B, process variations resulting in weaker NMOS current drive may result in output node being pulled down through MN1 slower than it is pulled up through MP1 (resulting, e.g., in a faster charge rate). Either case results in a skew (tSKEW) between rise time (tRISE) and fall time (tFALL) which must be accounted for in the corresponding specified setup/hold time of the output signal OUT. As device frequencies increase, it is essential to minimize such skew.
One method to minimize such skew is to utilize a circuit compensation scheme, for example, in an effort to speed up slower devices while slowing faster devices to match one another in speed and drive strength. A common compensation scheme is illustrated in FIG. 3. A compensating device (MPC 302) is connected to a known resistor RA 304. The voltage drop (VA) at RA is fed to an operational amplifier 306. The amplifier 306 compares this voltage (VA) to that of a reference voltage (VREF). Thus, depending on the process, the output voltage of the amplifier (VBIAS) is generated such that VA matches VREF. VBIAS can then be used to bias various P-type transistors in OCDs across a common chip. As illustrated in FIG. 3B, a similar compensating circuit 320 can also be used to compensate N-type transistors, utilizing an N-type compensating device MNC 322 and a known resistor RB 324 connected to an operational amplifier 326.
Unfortunately, before the compensating voltage VBIAS can be used, it has to be distributed on the chip to each OCD or other circuits which need to be compensated. To reduce noise resulting from coupling to other digital lines, lines carrying VBIAS should be closely shielded. As a result, the distribution of VBIAS may consume a significant amount of available routing space. The increased current may result in substantial increases in power consumption and determining the proper values of VREF and the resistors (RA and RB) may require substantial testing. Further, process variations may make it difficult to accurately control the values of RA and RB, consequently making it difficult to accurately control the bias voltage.
Accordingly, there is a need for an improved off-chip driver circuit (OCD) that is less sensitive to process variations than conventional OCDs.